Integrated circuit structures with spin torque transfer magnetic random access memory having increased memory cell density and methods for fabricating the same

ABSTRACT

STT-MRAM integrated circuit and method for fabricating the same are disclosed. An integrated circuit includes a word line layer, a bit line layer, and an MRAM stack in contact with the bit line metal layer. The integrated circuit further includes a first doped silicon layer in contact with the MRAM stack, the first doped silicon layer including conductivity-determining ions of a first type, and a second doped silicon layer in contact with the first doped silicon layer and further in contact with the word line layer, the second doped silicon layer including conductivity-determining ions of a second type that is opposite the first type. Still further, the integrated circuit includes a third doped silicon layer in contact with the second doped silicon layer and a source line layer in electrical contact with the third doped silicon layer.

TECHNICAL FIELD

The present disclosure generally relates to integrated circuits andmethods for fabricating integrated circuits. More particularly, thepresent disclosure relates to spin torque transfer magnetic randomaccess memory (STT-MRAM) structures in integrated circuits withincreased memory cell density and methods for fabricating the same.

BACKGROUND

Magnetic Random Access Memory (MRAM) is a non-volatile computer memorytechnology based on magnetoresistance. MRAM differs from volatile RandomAccess Memory (RAM) in several respects. Because MRAM is non-volatile,MRAM can maintain memory content when the memory device is not powered.Though non-volatile RAM is typically slower than volatile RAM, MRAM hasread and write response times that are comparable to that of volatileRAM. Unlike typical RAM technologies that store data as electriccharges, MRAM data is stored by magnetoresistive elements. Generally,the magnetoresistive elements are made from two magnetic layers, each ofwhich holds a magnetization. The magnetization of one layer (the “pinnedlayer”) is fixed in its magnetic orientation, and the magnetization ofthe other layer (the “free layer”) can be changed by an externalmagnetic field generated by a programming current. Thus, the magneticfield of the programming current can cause the magnetic orientations ofthe two magnetic layers to be either parallel, giving a lower electricalresistance across the layers (“0” state), or antiparallel, giving ahigher electrical resistance across the layers (“1” state). Theswitching of the magnetic orientation of the free layer and theresulting high or low resistance states across the magnetic layersprovide for the write and read operations of the typical MRAM cell.

Though MRAM technology offers non-volatility and faster response times,the MRAM cell is limited in scalability and susceptible to writedisturbances. The programming current employed to switch between higherand lower electrical resistance states across the MRAM magnetic layersis typically high. Thus, when multiple cells are arranged in an MRAMarray, the programming current directed to one memory cell may induce afield change in the free layer of an adjacent cell. This potential forwrite disturbances, also known as the “half-select problem,” can beaddressed using a spin torque transfer technique.

A conventional spin torque transfer MRAM (STT-MRAM) cell may include amagnetic cell stack, which may be a magnetic tunnel junction (MTJ). AnMTJ is a magnetoresistive data storing element including two magneticlayers (one pinned and one free) and an insulating layer in between thetwo magnetic layers; a bit line, a word line; a source line; and anaccess transistor. A programming current typically flows through theaccess transistor and the magnetic cell stack. The pinned layerpolarizes the electron spin of the programming current, and torque iscreated as the spin-polarized current passes through the stack. Thespin-polarized electron current interacts with the free layer byexerting a torque on the free layer. When the torque of thespin-polarized electron current passing through the stack is greaterthan the critical switching current density (JO, the torque exerted bythe spin-polarized electron current is sufficient to switch themagnetization of the free layer. Thus, the magnetization of the freelayer can be aligned to be either parallel or antiparallel to the pinnedlayer, and the resistance state across the stack is changed.

The STT-MRAM has advantageous characteristics over the MRAM, because thespin-polarized electron current eliminates the need for an externalmagnetic field to switch the free layer in the magnetoresistiveelements. Further, scalability is improved as the programming currentdecreases with decreasing cell sizes, and the writing disturbance andhalf-select problem is addressed. Additionally, STT-MRAM technologyallows for a higher tunnel magnetic resistance ratio, meaning there is alarger ratio between higher and lower electrical resistance states,thereby improving read operations in the magnetic domain.

Presently-known STT-MRAM structures and methods for fabricating suchstructures all suffer from several drawbacks. For example, the switchcurrent required to switch the magnetization direction of the MTJelement from parallel to anti-parallel is 20-50% larger than thatrequired to switch from anti-parallel to parallel. Furthermore, in aconventional STT MTJ element (1 transistor, +1 MTJ), the largerparallel-to-anti-parallel switching current is limited by “sourcedegeneration” or the so called “source-site loading” effect. This sourcedegeneration effect constrains the amount of current flowing through theMTJ element and may prevent the MTJ element from switching themagnetization direction from anti-parallel to parallel reliably.Accordingly, it is desirable to have an STT MTJ element that is notlimited by the source degeneration effect to ensure reliable switchingof the magnetization direction of the MTJ element from parallel toanti-parallel.

One particular solution to the source degeneration problem has beenproposed by Liu et al., U.S. Pat. No. 8,416,600 B2 (issued Apr. 9,2013). Liu et al. propose connecting the bit line with the fixed layer,and the free layer with the drain of the switching device (Liu et al.,FIG. 3). This configuration is implemented either using afour-metallization-layer stack (Liu et al., FIG. 5) or a reversal of theMTJ free and fixed layers (Liu et al., FIG. 6). However, thefour-metallization-layer stack requires a large amount of space toimplement, which is impractical for many newer devices that have tightspacing requirements, and the reversal of the MTJ free and fixed layershave proven to result in poor fixed layer quality due to over-etchingthereof.

Over recent years, there has been a constant drive to reduce thephysical size of various consumer electronic products that employintegrated circuits. The demand for smaller consumer products withgreater capability has resulted in the scaling or reduction in thephysical size of integrated circuit devices that are employed in suchconsumer products. The reduction in size of the integrated circuits hasbeen achieved by, among other things, reducing the physical size of thevarious semiconductor devices, e.g., the memory cells, and by greatlyincreasing the density of such cells in a given area. As noted above,the solutions proposed by Liu et al. to prevent the source degenerationproblem are not capable of conforming to the paradigm of reduction inphysical size.

Accordingly, it is desirable to provide robust and reliable STT-MRAMstructures. Additionally, it is desirable to provide methods for thefabrication of such structures that are easily integrated into existingprocess flow schemes used in semiconductor fabrication facilities. Stillfurther, it is desirable to provide such structures and methods thatprevent the source degeneration problem while maintaining a small cellsize suitable for use in modern consumer electronic devices.Furthermore, other desirable features and characteristics of the presentdisclosure will become apparent from the subsequent detailed descriptionand the appended claims, taken in conjunction with the accompanyingdrawings and the foregoing technical field and background.

BRIEF SUMMARY

Spin torque transfer magnetic random access memory in integratedcircuits and methods for fabricating the same are disclosed. In oneexemplary embodiment, an integrated circuit includes a word line layer,a bit line metal layer, and an MRAM stack including an MTJ layer incontact with the bit line metal layer. The integrated circuit furtherincludes a first doped silicon layer and a spacer structure thatseparates the MTJ layer of the MRAM stack from the first doped siliconlayer, the first doped silicon layer including conductivity-determiningions of a first type, and a second doped silicon layer in contact withthe first doped silicon layer and further in contact with the word linemetal layer, the second doped silicon layer includingconductivity-determining ions of a second type that is opposite thefirst type. Still further, the integrated circuit includes a third dopedsilicon layer in contact with the second doped silicon layer, the thirddoped silicon layer including conductivity-determining ions of the firsttype, and a source line layer in electrical contact with the third dopedsilicon layer.

In another exemplary embodiment, a method for fabricating an integratedcircuit includes forming a word line layer, forming a bit line layer,and forming a magnetic random access memory (MRAM) stack that includes atop electrode, a bottom electrode, and an MTJ layer in contact with thebit line metal layer. The method further includes forming a first dopedsilicon layer in contact with the top electrode of the MRAM stack and aspacer structure separating the MTJ layer of the MRAM stack from thefirst doped silicon layer, the first doped silicon layer includingconductivity-determining ions of a first type and forming the firstdoped silicon layer into small strips of cell regions. Further, themethod includes depositing an interlayer dielectric layer, CMP, andforming a trench through the first doped silicon layer to expose an endportion of the first doped silicon layer, thereby defining a series ofcells by forming Still further, the method includes forming a seconddoped silicon layer in contact with the end portion of the first dopedsilicon layer and further in contact with the word line layer, thesecond doped silicon layer including conductivity-determining ions of asecond type that is opposite the first type, forming a third dopedsilicon layer in contact with the second doped silicon layer, the thirddoped silicon layer including conductivity-determining ions of the firsttype, and forming a source line layer in electrical contact with thethird doped silicon layer.

In yet another exemplary embodiment, an integrated circuit includes aword line layer, a bit line layer, an interlayer dielectric (ILD) layerseparating the word line layer from the bit line layer, a bottomelectrode in contact with the bit line layer, a fixed layer in contactwith the bottom electrode, a barrier layer in contact with the fixedlayer, a free layer in contact with the barrier layer and separated fromthe fixed layer by the barrier layer, and a top electrode in contactwith the free layer. The integrated circuit further includes an n-typefirst doped silicon layer in contact with the top electrode, the firstdoped silicon layer including an end portion spaced apart from the topelectrode, and a p-type second doped silicon layer in contact with theend portion of the first doped silicon layer, the word line layer, andthe ILD layer. Still further, the integrated circuit includes third,n-type doped silicon layer in contact with the second doped siliconlayer and a source line layer in electrical contact with the third dopedsilicon layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will hereinafter be described in conjunction withthe following drawing figures, wherein like numerals denote likeelements, and wherein:

FIGS. 1A-10 illustrate, in cross section, STT-MRAM structures andmethods for fabricating STT-MRAM integrated circuits in accordance withone embodiment of the present disclosure; and

FIGS. 11A-16 illustrate, in cross section, STT-MRAM structures andmethods for fabricating STT-MRAM integrated circuits in accordance withanother embodiment of the present disclosure.

DETAILED DESCRIPTION

The following detailed description is merely illustrative in nature andis not intended to limit the embodiments of the subject matter or theapplication and uses of such embodiments. Furthermore, there is nointention to be bound by any expressed or implied theory presented inthe preceding technical field, background, brief summary or thefollowing detailed description.

Embodiments of the present disclosure are generally directed to spintorque transfer magnetic random access memory (STT-MRAM) integratedcircuit structures and methods for fabricating the same. For the sake ofbrevity, conventional techniques related to integrated circuit devicefabrication may not be described in detail herein. Moreover, the varioustasks and process steps described herein may be incorporated into a morecomprehensive procedure or process having additional steps orfunctionality not described in detail herein. In particular, varioussteps in the manufacture of semiconductor-based transistors arewell-known and so, in the interest of brevity, many conventional stepswill only be mentioned briefly herein or will be omitted entirelywithout providing the well-known process details.

As used herein, it will be understood that when an element or layer isreferred to as being “on,” “connected to” or “coupled to” anotherelement or layer, it may be directly on, connected to, or coupled to theother element or layer, or intervening elements or layers may bepresent. Further, spatially relative terms, such as “beneath,” “below,”“lower,” “above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. It will beunderstood that the spatially relative terms are intended to encompassdifferent orientations of the device in use or operation in addition tothe orientation depicted in the figures. For example, if the device inthe figures is turned over, elements described as being “below” or“beneath” other elements or features would then be oriented “above” theother elements or features. Thus, the exemplary term “below” canencompass both an orientation of above and below. The device may beotherwise oriented (rotated 90 degrees or at other orientations) and thespatially relative descriptors used herein may likewise be interpretedaccordingly.

FIGS. 1A-10 illustrate, in a cross-sectional view and in a top view(with “A” designated Figures showing the cross-sectional view and the“B” designated Figures showing the top view), STT-MRAM integratedcircuit structures and methods for fabricating STT-MRAM integratedcircuit structures in accordance with various embodiments of the presentdisclosure. The partially-formed integrated circuit structureillustrated in FIGS. 1A and 1B includes two metal layers 101, 103. Metallayers 101, 103 may be oriented substantially perpendicularly to oneanother. Further, each of metal layers 101, 103 may be provided in theform of a series of parallel metal “lines,” as shown particularly withregard to metal layer 103 in FIG. 1B. Accordingly, each of the metallines of metal layer 101 is substantially parallel to each of the meallines of metal layer 103. In an embodiment, the metal layer 101functions as a word line and the metal layer 103 functions as a bit lineof the STT-MRAM structure to be formed. The metal layers 101, 103 may beprovided within and/or above an inter-layer dielectric (ILD) layer 102,separating the metal layers 101, 103 from each other and from othermetal layers of the integrated circuit structure. By the term “within,”it is meant that the metal layers 101, 103 are embedded in the ILD layer102, wherein, optionally, a top surface of the bit line metal layer 103is substantially coplanar with a top surface of the ILD layer 102, andthe bit line metal layer 103 extends downward into the ILD layer 102(the coplanar top surface may be achieved by a planarization process,such as chemical mechanical planarization, performed after thedeposition of the metal material for metal layer 103, as will bedescribed in greater detail below). The ILD layer 102 may be formed ofone or more low-k dielectric materials, un-doped silicate glass (USG),silicon nitride, silicon oxynitride, or other commonly used materials.The dielectric constants (k value) of the low-k dielectric materials maybe less than about 3.9, for example, less than about 2.8. The metallayers 101, 103 may be formed of a conductive material, such as a metalor a metal alloy. In an embodiment, the metal layers are formed ofcopper, for example, and/or other commonly used conductive metals. Inone embodiment, the metal layers 101, 103 are in physical and electricalconnection with other metallization layers of the integrated circuit(not shown). In an alternate embodiment, the word line layer 101 is notformed of metal, but rather is formed from or as part of a semiconductorsubstrate.

The ILD 102 layer and the metal layer 101, 103 may be formed throughconventional techniques. For example, the layers 101, 103 may be formedusing photolithographic patterning and etching procedures. That is, aphotoresist layer is deposited and then is exposed to an image patternand treated with a developing solution to form pattern openings withinthe photoresist layer. With the openings thus formed, the substrate ILDlayer 102 may be etched to form parallel spaces therein. Thereafter, thematerial for the metal layers 101, 103 may be deposited usingconventional deposition techniques according to the particular materialselected, such as one of the various known vapor deposition processes.

Though not illustrated for simplicity in FIGS. 1A and 1B, the metallayers 101, 103 may be formed over other ILD and/or metallizationlayers, and also over an active region of a semiconductor substrateforming part of the integrated circuit structure. The bottom electrode112 may be formed during back-end-of-line processes (BEOL). For example,in one embodiment, the STT-MRAM feature according to the presentdisclosure may be formed during BEOL processes, for example between the2^(nd) and 3^(rd) metallization layers (M2/M3) of the device, althoughthe embodiments are not to be understood as limited to such. Thesubstrate may include a plurality of isolation features (not shown),such as shallow trench isolation (STI) features or local oxidation ofsilicon (LOCOS) features. The isolation features may define and isolatethe various microelectronic elements (not shown), also referred toherein as the aforesaid active regions. Examples of the variousmicroelectronic elements that may be formed in the substrate includetransistors (e.g., metal oxide semiconductor field effect transistors(MOSFET) and bipolar junction transistors (BJT)), and/or other suitableelements. This microelectronic element is used as a selector device foran exemplary STT-MRAM cell, as is known in the art.

With reference now to FIGS. 2A and 2B, three additional layers 106, 107,and 108 are deposited and patterned over the bit line metal layer 103.These three layers 106, 107, and 108 are patterned so as to be formed insegments that are wider than and centered over the bit line metal layer103 in the width direction (left to right in the cross-section of FIG.2A), with spaces between each segment in the width direction. In thelength direction (top to bottom in FIG. 2B), the three additional layers106, 107, and 108 are spaced at intervals along each line of the metallayer 103. Layer 106 is the bottom electrode of the STT-MRAM structureto be formed, layer 107 is the MTJ “stack” of the STT-MRAM structure tobe formed, and layer 108 is the top electrode of the STT-MRAM structureto be formed. The top and bottom electrode 106, 108 may independently beformed of a conductive metal, such as tantalum, tantalum nitride, and/ortitanium, for example. The MTJ stack layer 107 includes a pinned orfixed layer, a thin (i.e., about 1 to about 2 nm in thickness) oxidelayer as a barrier layer (such as silicon oxide or magnesium oxide, forexample), and a free layer (these layers of the MTJ stack are notseparately illustrated for ease of illustration). The fixed layer of theSTT-MRAM structure is formed (deposited) over an upper surface of thebottom electrode 106. In an exemplary embodiment, the fixed layer isformed of a platinum manganese (PtMn), iridium manganese (IrMn), nickelmanganese (NiMn), or iron manganese (FeMn) material, and may includeCoFeB. The free layer may be formed of CoFeB, for example. For example,in a particular embodiment, the “stack” of material layers may be asfollows, from the bottom electrode 106 through a top electrode 108: aTaN bottom electrode layer, a Ta seed layer overlying the TaN bottomelectrode layer, a PtMn antiferromagnetic layer over the Ta seed layer,a CoFe pinned layer overlying the PtMn antiferromagnetic layer, an Rucoupling layer overlying the CoFe pinned layer, a CoFeB reference layeroverlying the Ru coupling layer, a MgO barrier layer overlying the CoFeBreference layer, a CoFeB free layer overlying the MgO barrier layer, aTa capping layer overlying the CoFeB free layer, and a TaN top electrodeoverlying the Ta capping layer.

As indicated in FIG. 2A, the segments of the three layers 106, 107, and108 may be collectively referred to as MRAM stacks 105. In alternativeembodiments, as opposed to the direct physical connection illustrated,stacks 105 could be connected to the respective bit line 103 by a via orother conductive structure. In further embodiments, the order of thefixed, barrier, and free layers of the MTJ stack layer 107 may bereversed, in which case the described order of the above examples wouldbe reversed. In alternative embodiments, the MRAM stacks 105 may bereplaced with RRAM, PCRAM, or any other memory element, as are known inthe art.

Turning now to FIGS. 3A and 3B, spacer structures are formed alongsidewalls of the MRAM stacks 105 to separate the MTJ 107 from the n-typesilicon so that the n-type silicon is only in contact with the topelectrode, followed by the deposition of a doped silicon layer 109 overan entirety of the substrate, including over the MRAM stacks 105,exposed bit line portions 103, and over the ILD layer 102. The dopedsilicon layer 109 may be formed of an amorphous silicon material or apolycrystalline silicon material. The doped silicon layer 109 may bedoped with conductivity-determining ions. In one exemplary embodiment,the layer 109 is doped with n-type conductivity-determining ions, as areknown in the art. The doped silicon layer 109 may be deposited as statedusing conformal deposition techniques such that it has a relativelyconsistent thickness over all surfaces of the ILD layer 102 and the MRAMstacks 105.

Thereafter, with attention now to FIGS. 4A and 4B, the doped siliconlayer 109 is patterned, using for example photolithographic masking andpatterning techniques as discussed above, into a plurality of dopedsilicon segments 109A. Each segment 109A covers an entirety of two MRAMstacks that are adjacent to one another in the width direction, as wellas the ILD layer 102 therebetween. The segments 109A are spaced apartfrom one another in both the width and length directions. Subsequent tothe patterning of the plurality of doped silicon segments 109, a furtherILD layer 110 is formed over an entirety of the substrate, includingover the segments 109A, exposed bit lines portions 103, and over the ILDlayer 102 as shown in FIGS. 5A and 5B. CMP is carried out to planarizethe ILD layer 201.

As noted above, the segments 109 extend over the ILD layer 102 betweentwo adjacent MRAM stacks 105. With reference now to FIG. 6, trenches 111are formed (for example, using photolithographic patterning andanisotropic etching) between these adjacent MRAM stacks 105 and throughthe doped silicon layer segments 109A that extends therebetween. In thewidth direction, therefore, the segments 109A are split in two parts bythe formation of such trenches 111, resulting in a plurality of dopedsilicon segments 109B. Accordingly, over alternating bit lines 103, thesegments 109B are separated either by a trench 111 or the ILD layer 110.The trenches 111 are formed through the ILD layer 110, the doped siliconsegments 109A, and through the ILD layer 102, stopping on the word line101 and exposing portions of the word line 101 at the bottom of thetrenches 111. With the trenches thus formed in the ILD layers 110, 102as well, the lower ILD layer 102 is separated into a plurality ofsegments 102A, and the upper ILD layer 110 is separated into a pluralityof segments 110A, which are separated from one another in the widthdirection as shown in the cross-section in FIG. 6. Each such segment102A, 110A encompasses two MRAM stacks 105 and two of the doped siliconsegments 109B thereover.

Turning now to FIG. 7, three additional layers 112, 113, and 114 aredeposited over the ILD layer segments 110A and within the trenches 111in a conformal manner. The layer 112 is a further doped silicon layerthat is doped using conductivity determining ions of the opposite typeas layer 109. For example, in the exemplary embodiment wherein layer 109was formed using n-type doping ions, layer 112 is formed using p-typedoping ions. The layer 112, as with layer 109, may be formed of a dopedamorphous silicon or polycrystalline silicon material, and may be formedconformally over the ILD segments 110A and within the trenches 111. Asshown, the layer 112 comes in direct contact with the exposed portionsof the word line metal layer 101 at the bottom of trenches 111, as wellsas an end of doped silicon segments 109B that are exposed at thesidewalls of the trenches 111. The layer 113 is yet a further dopedsilicon layer that is doped using conductivity determining ions of theopposite type as layer 112 (i.e., the same type as layer 109). Forexample, in the exemplary embodiment wherein layer 109 was formed usingn-type doping ions, layer 113 is also formed using n-type doping ions.The layer 113, as with layer 109, may be formed of a doped amorphoussilicon or polycrystalline silicon material, and may be formedconformally over the ILD segments 110A and within the trenches 111.Layer 114 is a metal layer that may act as a source line for theSTT-MRAM structures to be formed in the integrated circuit. Blanketdeposition techniques may be used to deposit layer 114, whichaccordingly fills any remaining open portions of the trenches 111 notfilled by layers 112 and 113, as well as being deposited to a thicknessover the ILD segments 110A. Layer 114 may be formed of a suitableconductive material, such as copper or other materials as are known inthe art.

FIG. 7 thus illustrates an embodiment of a STT-MRAM structure inaccordance with the present disclosure exhibiting a reduced spacerequirement or reduced “footprint” as compared to structures previouslyknown in the art. Beneficially, the disclosed structure protects againstthe above-described source degeneration effect with the bit line metallayer 103 being provided in series with the fixed layer of the MTJ stack107, and the source line metal layer 114 being in series with the freelayer of the MTJ stack 107 (with the word line metal layer 101functioning as a gate of a transistor between the source line 114 andthe free layer of the MTJ stack 107). The p-n junction diode formedbetween layers 112, 113, and 114 regulates the direction of flow ofcurrent upon application of current to the source line 114.

In another embodiment in accordance with the present disclosure as shownin FIG. 8, the function of the source line metal layer 114 may beintegrated with the doped silicon layer 113. That is, instead ofconformal deposition of the layer 113 as shown in FIG. 7, a layer 113Amay be formed using blanket deposition techniques to fill any remainingportions of the trenches 111 not filled by layer 112. The doping andcomposition of layer 113A are the same in all other aspects as describedabove with regard to the formation of layer 113.

In yet another embodiment in accordance with the present disclosure asshown in FIG. 9, the word line may be formed extending parallel (asopposed to perpendicularly) to the bit line. In order to ensure contactbetween the p-n diode and the word line, a layer 112A is formed in placeof layer 112, wherein layer 112A extends underneath ILD segments 102A tofor direct physical contact with the word line 101A. A further ILD layer115 is provided to insulate the word line 101A. The trench 111 may beextended to the ILD layer 115, and may contact with a repositionedsource line 114A positioned below the ILD layer 115.

The process to form the structure of FIG. 9 is as follows. Source lineor substrate 114A is formed extending in one direction, as shown. ThenILD 115 is formed over source line 114A. Word line 101A is formedperpendicularly to the source line 114A. P-type silicon 112A is formedextending over the word line 101A and the ILD 115. Then, further ILDfollowed by bit line, which is parallel to the word line, MRAM stack,spacers, first silicon layer, and still further ILD is formed. Trench111 is then etched to define cells, the etch extending into the p-typesilicon layer 112A. Further conformal p-type silicon material isdeposited over the top ILD layer and along the sidewalls of the trench111 to form a continuous p-type silicon layer. This is followed byfurther etching the trench into ILD 115 to contact with the source line114A, and deposition of n-type silicon to fill the trench and contactwith the p-type silicon and the source line 114A, resulting in astructure as shown in FIG. 9.

In still a further embodiment in accordance with the present disclosureas shown in FIG. 10, a source line 114B may be positioned above thedoped silicon layers as in FIG. 7, while still using the parallelbit/source lines as in FIG. 9. In this embodiment, a layer 113 of dopedsilicon with the same doping type as the segments 109B extendsconformally to the bottom of the trenches 111, with a source line metallayer 114B providing the fill to fill any remaining portions of thetrenches 111, as described above with regard to FIG. 7.

Various embodiments of the present disclosure may also be modified toaccommodate multiple layers of MRAM structures, as shown in connectionwith FIGS. 11 through 16. The process steps shown in FIG. 11 areperformed after those described above in connection with FIGS. 1Athrough 5B, which are not repeated herein for brevity. In FIG. 11, theprocess disclosed above with regard to FIGS. 1A through 5B is repeatedone or more times to form a plurality of MRAM layers, three of which,201, 202, and 203 are shown in FIG. 11. As shown in FIG. 12, theelongated trenches 111A are formed all the way through each of thelayers 201, 202, and 203 to expose portions of the word line metal layer101, analogously to the process shown in FIG. 6, with the differencebeing that the etch to form the trenches extends deeper so as to passthrough each of layers 201, 202, and 203. Further, as shown in FIG. 13,layers 112B, 113D, and 114C are formed analogously to layers 112, 113,and 114 shown in FIG. 7, with the difference being that each layerextends vertically a greater distance to extending downward through theelongated trenches 111A for physical and electrical contact with each ofthe segments 109B of each respective layer 201, 202, and 203, as well asfor physical and electrical contact with the source line 101.

Furthermore, FIGS. 14, 15, and 16 provide analogous embodiments to thoseshown in FIGS. 8, 9, and 10, respectively, with application to multiplelayers 201, 202, and 203. As the same numbering convention is used witheach such embodiment, further description thereof need not be providedherein.

While at least one exemplary embodiment has been presented in theforegoing detailed description, it should be appreciated that a vastnumber of variations exist. It should also be appreciated that theexemplary embodiment or exemplary embodiments are only examples, and arenot intended to limit the scope, applicability, or configuration of theinvention in any way. Rather, the foregoing detailed description willprovide those skilled in the art with a convenient road map forimplementing the exemplary embodiment or exemplary embodiments. Itshould be understood that various changes can be made in the functionand arrangement of elements without departing from the scope of theinvention as set forth in the appended claims and the legal equivalentsthereof.

What is claimed is:
 1. An integrated circuit comprising: a word linelayer; a bit line layer; a magnetic random access memory (MRAM) stack incontact with the bit line metal layer; a first doped silicon layer incontact with the MRAM stack, the first doped silicon layer comprisingconductivity-determining ions of a first type; a second doped siliconlayer in contact with the first doped silicon layer and further incontact with the word line layer, the second doped silicon layercomprising conductivity-determining ions of a second type that isopposite the first type; a third doped silicon layer in contact with thesecond doped silicon layer; and a source line layer in electricalcontact with the third doped silicon layer.
 2. The integrated circuit ofclaim 1, wherein the third doped silicon layer comprises conductivityions of the first type.
 3. The integrated circuit of claim 2, whereineach of the word line layer, bit line layer, and source line layerscomprise a metal material.
 4. The integrated circuit of claim 1, whereinthe source line layer comprises a third doped silicon layer in contactwith the second doped silicon layer, the third doped silicon layercomprising conductivity ions of the first type.
 5. The integratedcircuit of claim 4, wherein the word line layer and the bit line layerscomprise a metal material.
 6. The integrated circuit of claim 1, whereinthe MRAM stack comprises a top electrode, a magnetic tunnel junction(MTJ) stack, and a bottom electrode, or, alternatively, wherein the MRAMstack is replaced with an RRAM, PCRAM, or any other memory element. 7.The integrated circuit of claim 6, wherein the MTJ stack comprises afixed layer, a free layer, and a barrier layer between the fixed layerand the free layer.
 8. The integrated circuit of claim 1, wherein thefirst doped silicon layer comprises a plurality of discontinuoussegments, each such segment being in contact with one MRAM stack.
 9. Theintegrated circuit of claim 1, wherein the word line layer extendssubstantially perpendicularly with respect to the bit line layer. 10.The integrated circuit of claim 9, further comprising a first interlayerdielectric (ILD) layer below the first doped silicon layer and a secondILD layer above the first doped silicon layer, wherein the first dopedsilicon layer and the first and second ILD layer form a common sidewallthat extends vertically above the word line layer, and wherein thesecond doped silicon layer is formed along the common sidewall along thefirst doped silicon layer and the first and second ILD layers.
 11. Theintegrated circuit of claim 10, wherein the source line layer extendsparallel to the common sidewall and is separated from the commonsidewall by the third doped silicon layer.
 12. The integrated circuit ofclaim 1, wherein the word line layer extends substantially parallel withrespect to the bit line layer.
 13. The integrated circuit of claim 12,further comprising a first interlayer dielectric (ILD) layer below thefirst doped silicon layer and a second ILD layer above the first dopedsilicon layer, wherein the first doped silicon layer and the first andsecond ILD layer form a common sidewall that extends vertically abovethe word line layer, and wherein the second doped silicon layer isformed along the common sidewall along the first doped silicon layer andthe first and second ILD layers as well as underneath the first dopedsilicon layer in contact with the word line layer.
 14. The integratedcircuit of claim 13, wherein the source line layer extends parallel tothe common sidewall and is separated from the common sidewall by thesecond doped silicon layer.
 15. The integrated circuit of claim 13,further comprising a third ILD layer beneath the word line layer,wherein the source line layer extends beneath the third ILD layer, andfurther comprising a third doped silicon layer in contact with thesource line layer and extending parallel to the common sidewallseparated from the common sidewall by the second doped silicon layer,the third doped silicon layer comprising conductivity ions of the firsttype.
 16. The integrated circuit of claim 1, wherein the firstconductivity-determining ion type is n-type and the secondconductivity-determining ion type is p-type.
 17. A method forfabricating an integrated circuit comprising: forming a word line layer;forming a bit line layer; forming a magnetic random access memory (MRAM)stack in contact with the bit line metal layer; forming a spacerstructure surrounding the MRAM stack; forming a first doped siliconlayer in contact with the MRAM stack, the first doped silicon layercomprising conductivity-determining ions of a first type; forming atrench through the first doped silicon layer to expose an end portion ofthe first doped silicon layer; forming a second doped silicon layer incontact with the end portion of the first doped silicon layer andfurther in contact with the word line layer, the second doped siliconlayer comprising conductivity-determining ions of a second type that isopposite the first type; forming a third doped silicon layer in contactwith the second doped silicon layer; and forming a source line layer inelectrical contact with the third doped silicon layer.
 18. The method ofclaim 17, further comprising forming a first interlayer dielectric (ILD)layer below the first doped silicon layer and a second ILD layer abovethe first doped silicon layer, wherein forming the trench comprisesforming a trench through the first and second ILD layers in addition tothrough the first doped silicon layer, and wherein forming the seconddoped silicon layer comprises forming a second doped silicon layer alongthe first and second ILD layers within the trench.
 19. The method ofclaim 17, wherein forming the first doped silicon layer comprisesforming an n-type doped silicon layer, and wherein forming the seconddoped silicon layer comprises forming a p-type doped silicon layer. 20.An integrated circuit comprising: a word line layer; a bit line layer;an interlayer dielectric (ILD) layer separating the word line layer fromthe bit line layer a bottom electrode in contact with the bit linelayer; a fixed layer in contact with the bottom electrode; a barrierlayer in contact with the fixed layer; a free layer in contact with thebarrier layer and separated from the fixed layer by the barrier layer; atop electrode in contact with the free layer an n-type first dopedsilicon layer in contact with the top electrode, the first doped siliconlayer comprising an end portion spaced apart from the top electrode; ap-type second doped silicon layer in contact with the end portion of thefirst doped silicon layer, the word line layer, and the ILD layer; ann-type third doped silicon layer in contact with the second dopedsilicon layer; and a source line layer in electrical contact with thethird doped silicon layer.